Portable products, such as personal computers, digital cameras, and portable phones, have recently been used widely, and demanded to have small sizes, low profiles, light weights, higher resolution, and more functions. In order to satisfy the demands, semiconductor devices have been had their packages having small sizes and low profiles and mounted in a solid or three-dimensional manner. In order to easily provide packages having low profiles and the three-dimensional mounting, a cavity board has been known.
FIG. 15 is a cross-sectional view of conventional circuit board 27 disclosed in Patent Documents 1 and 2. Lower sub-board 22 and upper sub-board 23 are stacked via connection layer 21 while electrodes and windows are positioned. Then, lower sub-board 22 and upper sub-board 23 are heated and pressed to be bonded to each other, thereby providing circuit board 27 having a recess in which an electronic component is accommodated. Connection layer 21 is made of, for example, mixture of thermosetting resin and inorganic filler.
In conventional circuit board 27, the process for stacking sub-boards 22 and 23 and connection layer 21 while heating and pressurizing sub-boards 22 and 23 and connection layer 21 decreases viscosity of the thermosetting resin included in connection layer 21 to allow the thermosetting resin to flow generally from the board to an outside of the board. Upon the thermosetting resin flowing, the inorganic filler of connection layer 21 flows together with the thermosetting resin. Thus, particles of the inorganic filler are extruded from connection layer 21. The extruded particles of the inorganic filler are attached onto and remain on a surface of board 27 as dust and foreign material. The remaining particles may drop after board 27 is completed, thereby contaminating the surface of board 27.
The inorganic filler itself does not have adhesiveness. If particles of the inorganic filler flow near an edge of connection layer 21, sub-boards 22 and 23 are not sufficiently adhered to connection layer 21, accordingly peeling sub-boards 22 and 23 from connection layer 21 or producing cracks.
The inorganic filler flowing from connection layer 21 reduces a thickness of the edge of connection layer 21, accordingly causing connection layer 21 to have a curved surface. Upper sub-board 23 is joined to connection layer 21 along the surface of connection layer 21 while warping, and thus, always receive an internal stress in a direction along which upper sub-board 23 is peeled from connection layer 21. This internal stress decreases adhesion strength between connection layer 21 and upper sub-board 23.
Connection layer 21 including the thermosetting resin has a temperature rising, melts, and cures, thereby adhering to sub-boards 22 and 23. The stress becomes zero at a temperature at which connection layer 21 adheres to sub-boards 22 and 23. Then, while connection layer 21 cools sub-boards 22 and 23, an internal stress is applied to connection layer 21 and sub-boards 22 and 23 since connection layer 21 and sub-boards 22 and 23 have different heat shrinkage amounts. This stress may cause completed circuit board 27 to warp.
Circuit boards have been demanded to have semiconductor devices, such as LSIs, mounted densely, to have multilayer structure inexpensively. In order to realize the circuit board having the multilayer structure, plural wiring patterns provided in different layers at fine pitches are electrically connected to each other reliably.
For the connection of layers formed with a fine pitch as described above, an inner-via-hole (IVH) structure disclosed in Patent Documents 3 and 4 are used instead of through-holes having inner walls and metal-plated conductors on the walls.
FIG. 16A is a cross-sectional view of conventional circuit board 501 having the IVH structure. Circuit board 501 includes insulating board 502 having through-hole 503, via-conductor 504 made of conductive paste filling through-hole 503, and wiring patterns 505 provided on both surfaces of insulating board 502. Via-conductor 504 connects wiring patterns 505 on both surfaces. This structure can locate via-conductor 504 beneath a land to be connected to a component, hence providing circuit board 501 with a small size and allows components to be mounted densely.
FIG. 16B is a cross-sectional view of conventional circuit board 501 which is pressurized. When circuit board 501 is pressurized while through-hole 503 filled with conductive paste, the diameter of through-hole 503 may increase in the vicinity of both surfaces of insulating board 502, and may cause the filled conductive paste to flow over both surfaces of insulating board 502, thus causing via-conductor 504 to deform. The flowing conductive paste prevents via-conductor 504 from being connected to wiring patterns 505 stably. The deformation of via-conductor 504 increases the diameter of via-conductor 504 at both surfaces of insulating board 502, thus preventing via-conductor 504 from being fine. In this case, wiring pattern 505 may not be arranged finely and densely.
Patent Document 1: JP 2004-253774A
Patent Document 2: JP 2001-244368A
Patent Document 3: JP 6-268345A
Patent Document 4: JP 2002-208763A